Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors

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Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors
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  Thread Relocation:   A Runtime Architecture forTolerating Hard Errors in Chip Multiprocessors Omer Khan,  Member  ,  IEEE  , and Sandip Kundu,  Fellow  ,  IEEE  Abstract —As the semiconductor industry continues its relentless push for nano-CMOS technologies, device reliability and occurrenceof hard errors have emerged as a dominant concern in multicores. Although regular memory structures are protected against harderrors using error correcting codes or spare rows and columns, many of the structures within the cores are left unprotected. Even if thelocation of hard errors is known a priori, disabling faulty cores results in a substantial performance loss. Several proposed techniquesuse  microarchitectural redundancy   to allow defective cores to continue operation. These techniques are attractive, but limited due toeither added cost of additional redundancy that offers no benefits to an error-free core, or limited coverage, due to the naturalredundancy offered by the microarchitecture. We propose to exploit the  intercore redundancy   in chip multiprocessors for hard-errortolerance. Our scheme combines hardware reconfiguration to ensure reduced functionality of cores, and a runtime layer of software( microvisor  ) to manage mapping of threads to cores. Microvisor observes the changing phase behavior of threads and initiates threadrelocation to match the computational demands of threads to the capabilities of cores. Our results show that in the presence ofdegraded cores, microvisor mitigates performance losses by an average of two percent. Index Terms —Chip multiprocessor (CMP), hard-error tolerance, hardware/software codesign, hypervisor, virtualization. Ç 1 I NTRODUCTION T RANSISTOR scaling hasenabledintegrationofanexponen-tially increasing number of devices. It is widely believedthat Chip Multiprocessors (CMP) will allow a clear path toITRS technology scaling projections of 100 billion transistorsperchipbyyear2020[1].Intheareaofcomputing,availabilityof an ever-increasing number of transistors has generallytranslated to additional resources. However, due to circuitreliability and marginality problems, the susceptibility of these resources to permanent errors has also grown.Hard errors can occur at manufacturing time or in thefield at runtime. Faults detected during manufacturinggenerally result in yield loss at the die or chip level.Assuming errors can be detected in the field using a faultdetection and isolation mechanism [2], [3], [4], [5], [6],disabling defective cores can result in a substantial perfor-mance loss. A desirable alternative is to allow the defectivecores within a CMP to continue operation, perhaps atreduced functionality. Proposed techniques use  microarchi-tecturalredundancy  bydisablingdefectiveexecutionpipelines[7] or redirecting execution to spare or alternate resources,thus avoiding the use of defective components [8], [9], [10].Although these techniques are attractive, they have twomajor drawbacks. First, they require changes to the micro-architecture, thus introducing design complexity. Second,the coverage of these techniques is limited to the naturalredundancy offered by superscalar cores. Most of the largestructures in cores do not offer redundancy to supportperformance enhancements. Examples of large structuresinclude integer multiplier and divider, floating point (FP)execution units, instruction decoders, and small array-likestructures such as Reorder buffer, Load Store Queues, andVirtual Registers. Adding spare resources to cover suchnonredundant structures amounts to added complexity andincreased area, while offering no benefits (performance orpower) to an error-free core.Inthispaper,wepresentanovelsystem-levelarchitecturethat exploits the natural  intercore redundancy  in chip multi-processors to tolerate the occurrence of hard errors. Ourarchitecture proposes a runtime mechanism to expose thecomputational demands of threads to the system, whichsubsequently uses this information to relocate threadsamong the fully functional and degraded cores. We showthatsystemperformancelossesduetotheoccurrenceofharderrors in single or multiple cores can be mitigated withminimal changes to the hardware and software abstractionlayersintoday’ssystems.Asourschemeisappliedatthecorelevel, it covers a significant area of the cores including largeexecution units, array structures, and combinational logicsuch as decoder unit. The main features of our proposedscheme are: Exposing computational demands of threads . As ourscheme relies on phase classification within threads,runtime hardware to observe implementation-independentinformation is useful. We present a phase classificationscheme based on tracking execution frequencies of   instruc-tion types  at an interval granularity. We show that ourInstruction-Type Vectors (ITVs) reveal the computationaldemands of phases by exposing the instruction-typedistributions. This information is used for tuning of threadsto cores mapping, such that phaseswithin threadsthat incur IEEE TRANSACTIONS ON COMPUTERS, VOL. 59, NO. 5, MAY 2010 651 .  O. Khan is with the University of Massachusetts Amherst, 2 FenwickCircle, Framingham, MA 01701. E-mail: okhan@ecs.umass.edu. .  S. Kundu is with the University of Massachusetts Amherst, 309J KnowlesEngineering Building, 151 Holdsworth Way, Amherst, MA 01002.E-mail: kundu@ecs.umass.edu. Manuscript received 8 Nov. 2008; revised 17 Mar. 2009; accepted 6 May2009; published online 21 May 2009.Recommended for acceptance by C. Bolchini and D. Sciuto.For information on obtaining reprints of this article, please send e-mail to:tc@computer.org, and reference IEEECS Log Number TC-2008-11-0558.Digital Object Identifier no. 10.1109/TC.2009.76. 0018-9340/10/$26.00    2010 IEEE Published by the IEEE Computer Society  minimum performance loss when mapped to cores withreduced functionality, are relocated to the degraded cores. Managing threads to cores mapping . Insulating man-agement from the operating system enables a scalablesystem-level solution and allows our fault tolerance schemeto evolve freely. We assume an architected concealedsoftware ( microvisor ) that manages the matching of pro-gram phases to computational resources and dynamicallyadapts mapping of phases within threads to cores. Theunderlying mechanism to enable such mapping is fast andsecures thread migration. Performance maximization based on continuous man-agement . The main contribution of our proposed architec-ture is to enable hard-error tolerance in a CMP when faultsdisable or degrade capabilities of structures within cores.Benefits from our scheme are greatest when phases withinthreads are continuously evaluated for mapping threads tocores, such that the system availability is optimized atminimal performance loss. Our results show that micro-visor enables functional execution in CMPs with an averageof two percent performance loss, compared to an average of 20 percent loss in performance due to disabling faulty cores.The rest of the paper is organized as follows: In Section 2,we provide background and motivation followed by adiscussion on related work in Section 3. A description of theproposed system architecture for hard-error tolerance ispresented in Section 4. Section 5 discusses our programphase classification scheme. Section 6 presents our experi-mental setup, and Section 7 presents the implementationdetailsofthemajorcomponentsofourarchitecture.Section8discusses the results and analysis of our experiments. Weconclude in Section 9. 2 B ACKGROUND AND  M OTIVATION Current design practice is to assume that the underlyinghardwarecontinuestobecorrectduringtheproductlifetime.However, relentless push for smaller devices and intercon-nects has moved the technology closer to a point where suchdesign paradigm is not valid [11]. For example, with theadvent of 90 nm technology, Negative Bias TemperatureInstability(NBTI)hasbecomeamajorreliabilityconcern[12],where a PMOS device degrades continuously with voltageand temperature stress. These problems are expected toworsen nano-CMOS technologies in future [13]. Designs aremore likely to fail due to what designers call PVT issues,namely process corner, voltage, and temperature issues. Themajorityofthesefaultswillappearunderspecificfrequency,voltage,temperature,andworkloadconditions.Itmaynotbepossible to screen all problems in the factory. They must bedealtwithafterwardsinthefieldtoassureadequateproductreliability [14], [15]. We argue that failure detection andsystem reconfiguration in the field will become necessary toassure adequate product reliability.Fault tolerance techniques are generally categorized intodetection/isolation followed by correction/recovery due toerrors. This paper focuses on the fault correction/recovery.Whilefaultdetection,diagnosis,andisolationareanecessarycomponent of any fault tolerance scheme and may requireadditional complexity, they are beyond the scope of thispaper. We focus on the system reconfiguration aspect of fault tolerance.In a CMP that experiences both “soft defects” andmultiple device failures, even when the system starts outwith symmetric homogeneous cores, as device failuresaccumulate, the system degenerates into a heterogeneousmulticore. An asymmetric CMP breaks one of the majorassumptions made by software developers; i.e., all coresprovide equal performance. Changing such assumptionsrequires a major change to system abstraction layers. Onecannot expect the operating system to keep adapting to theunderlying changes in the hardware. The major challenge isto accomplish fault tolerance by staying with the provenpath of architecture, software, and design paradigms. Thisis where our proposed architecture fits in. We proposecreating a highly reliable CMP through runtime configura-tion and reliability management that is not overly intrusiveon the design process such that the software, includingoperating system, is impervious to underlying changes.Modern chip multiprocessors devote a large fraction of die area to memory structures such as multilevel caches.Fortunately, caches are protected from hard errors usingspare rows and columns, and error detecting/correctingcodes [16]. This leaves the cores of the CMP susceptible tothe occurrence of hard errors.  Microarchitecture-redundancy - based techniques [7], [8], [9], [10] are shown to be effectivefor structures that have exploitable natural redundancy. Butmost of the large structures such as integer multiplier anddivider, floating point execution units, instruction decoders,and small noncache arrays are left susceptible to hard errorsin today’s systems. Our proposed scheme utilizes theinherent  intercore redundancy  in CMPs to cover occurrencesof hard errors in all structures of a core and does not requireadding spare or redundant units. 3 R ELATED  W ORK ON  H ARD -E RROR  T OLERANCE The idea of incorporating redundancy in processors for faulttolerance is well entrenched. Skivakumar et al. identifymicroarchitectural redundancy in an Alpha processor [8].They exploit redundancy by demapping failed executionunitsandcachesaswellasnoncachearraystructuressuchasreorder buffer and register files. They report high coverageandshowthatdisablingonlyoneortwoentriesinthereorder buffer incurs a minimum of one percent performance loss.They explore the possibility of using redundant units in aprocessor to improve manufacturing yield at the cost of performance degradation. Srinivasan et al. analyze theperformance impact of graceful degradation in performance by disabling redundant resources to improve lifetimereliability [9].Bower et al. show that enabling redundant rows,columns,andsubarraysinstructuressuchasreorder bufferscan be effectively used to mitigate performance losses [17].However, Koren et al. show that structural irregularity andtestability issues in logic and control units render themunsuitable for partial redundancy [18]. Hence, the entireunits need to be replicated to achieve fault tolerance. 4 A RCHITECTURE FOR  H ARD -E RROR  T OLERANCE The central component of our hard-error tolerance archi-tecture is  Microvisor , a layer of implementation-dependent 652 IEEE TRANSACTIONS ON COMPUTERS, VOL. 59, NO. 5, MAY 2010  software, codesigned with the hardware. The primaryfunction of Microvisor is to manage the mapping of threadsto cores in a CMP with faulty or degraded cores. Of interestis to match computational requirements of threads with thecapabilities of cores. Microvisor creates a mapping of threads to cores such that the system performance (orthroughput)isoptimized.Relocationofthreadsissupported by migrating threads between cores. By their very nature,system reconfiguration mechanisms are implementationdependent and cannot be easily managed by conventionalsoftware. Conventional software is designed to satisfy afunctional interface (Instruction Set Architecture and Appli-cation Binary Interface) that is intended to shield thesoftware from implementation details, not reveal them.The microvisor as envisioned in Fig. 1 resides in a region of physical memory that is concealed from all conventionalsoftware (including the operating system). 4.1 Microvisor Architecture Our proposed scheme has both hardware and softwarecomponents, as shown in Fig. 1.The hardware component isa phase classification unit in each core that classifies andcharacterizes occurrence of phaseswhena thread ismappedto the core. When a phase change is detected, a hardwareinterrupt is generated to invoke the microvisor software.Additionally, the hardware platform provides support forvirtualization features like expanded isolation, and mechan-isms for quick thread migration [19], [20]. As our architec-ture is designed for optimizing performance in the presenceof degraded cores due to occurrence of hard errors, weassume that reconfiguration knobs are available in eachcore to selectively shut off failed structures, but still allowfunctional compatibility. Details of hardware reconfigura-tions used for this study are discussed in Section 7.The software component of our scheme is the microvisorsoftware that runs natively as a privileged process on theCMP. We assume a thin Virtual Machine Monitor (VMM)running underneath the operating system, which is primar-ily used to enter and exit, as well as pass thread specificinformation to the Microvisor [20]. Microvisor softwaremaintains severaldatastructuresfor managingthe mappingof threads to cores. Based on phase specific computationaldemands of threads captured via phase classification unit,and hard-error status of structures within individual cores,microvisor ranks the threads such that the computationaldemands of threads can be matched with the computecapabilities of cores. When microvisor finds a mapping suchthat the performance of the CMP can be optimized, itinvokes the thread migration procedure to swap the threadsrunning on the candidate cores. If microvisor evaluates noperformance gains by relocating threads to degraded cores,it simply exits.When microvisor is active, it has the highest privilegedaccess to the cores. When done, it exits via the VMM andpasses control back to the operating system. As a resultour approach delivers a hardware-software codesignedsolution that assists the system to adapt to the perfor-mance degradations due to faulty cores. 4.2 Related Work on Microvisor The proposed microvisor is inspired by IBM S/390 systemthat executes  millicode  for implementing complex ESA/390 instructions [21]. Millicode has access not only to allimplemented ESA/390 instructions but also to specialinstructions used to access specific hardware. Millicode isstored at a fixed location in the real memory and uses aseparate set of general purpose and control registers.Unlike millicode, the microvisor is completely hidden fromthe operating system leading to greater security, flexibility,and portability.The microvisor is similar in implementation and tech-nology to the hypervisor used in IBM systems that executesmillicode held in concealed memory. The main differenceis the objective—the hypervisor is directed “upward” atoperating system type functions. The microvisor, however,is directed downward at the microarchitecture- and im-plementation-dependent aspects of hardware implementa-tion. Thus, the microvisor, as perceived by us, operates beneath the ISA in concealed memory and can be changedwithout affecting software above the ISA.Transmeta Crusoe processor [22] demonstrated thepracticality of using codesigned virtual machines (VMs).Crusoe used VM technology for runtime binary translationfrom conventional x86 ISA to propriety VLIW-based ISA.Unlike Crusoe, we use VM technology for transparentmanagement of processor resources in software—function-ality orthogonal to binary translation. 4.3 Fault Detection and Isolation A key requirement for successful reconfiguration is detailedknowledge about locations of errors. Fault diagnosis andisolation at runtime is challenging because current archi-tectures lack fine-grain controllability and observability intothe microarchitecture state of the cores. This is a very activeresearch topic. Smolens et al. present an in-field early wear-out fault detection scheme that relies on the operatingsystem to switch between functional and scan mode to testthe chip in near-marginal conditions [3]. Bower et al. KHAN AND KUNDU:  THREAD RELOCATION:   A RUNTIME ARCHITECTURE FOR TOLERATING HARD ERRORS IN CHIP MULTIPROCESSORS 653 Fig. 1. Microvisor system view.  propose using small auxiliary cores that check committedinstructions for defect isolation [4]. BlackJack [5] exploitssimultaneously redundant threads on an SMT to detectdefects. Constantinides et al. propose a software-baseddefect detection and diagnosis technique, which is based onusing special firmware to periodically insert specificinstructions and tests for diagnosis [6]. An ACE-Enhancedarchitecture extends the existing scan chains using hier-archical, tree-structured organization to provide access tomicroarchitecture components.Microvisor periodically suspends CMP execution anduses special instructions to run directed tests for faultdetection and isolation. The time scales for optimizationsused by the microvisor to adapt threads to the capabilitiesof cores is much smaller (tens to hundreds of million cycles)than the probability of hard-error occurrences (days tomonths) [23]. Therefore, fault detection/isolation is not thefocus of this paper and assumed to be known a priori.The results of fault detection/isolation are stored in aFault Status Table (FST). FST maintains a status table foreach core and covered structures within the core. When astructure is found faulty, hardware reconfiguration routinesare initiated and the corresponding entry in the FST is set.For example, if a core has a degraded floating point unit, thecorresponding entry in the FST is set. FST is used to exposethe computational capabilities of cores to the microvisor. 4.4 Managing Threads to Cores Mapping The main data structures maintained by the microvisorsoftware are Threads to Cores Mapping Table (TCMT),Phase History Table (PHT), and FST. TCMT maintains thethreads to cores mapping of live threads in the system. Thepurpose of this table is to keep track of thread mapping, usethis information to assist with thread migration, and alsoinform the operating system of such actions.PHT has an entry for each live thread running in thesystem. For each thread entry, the PHT maintains the PastFootprints Table (PFT), which is discussed in further detailin Section 5.2. PFT keeps a track of classified stable phaseswithin threads along with the runtime characterized in-struction-type distribution of the phases, termed as ITV.When a thread is mapped to a core, the associated PFT isloaded into the core’s phase classification unit and updatedas the thread executes. Microvisor uses the classified ITV toexpose the computational demands of phases. Detailsof ITVare discussed in the following sections.As discussed in the previous section, FST keeps a trackof the reliability status of each core. Microvisor maintainsmemory mapped programmable thresholds that are used toassist in ranking the threads based on their computationaldemands. Details of thread ranking are discussed in thefollowing sections. The high-level software flow for themicrovisor is presented in Fig. 2.When the phase classification unit in any of the coresdetects a phase change, microvisor is invoked. On eachinvocation, microvisor first updates the PHT with latestclassified phase information. The predicted phase informa-tion for all threads is now sent to a Rank and NormalizeUnit (RNU). RNU ranks the computational requirementsof expected phase for each thread, and in conjunction withcomputational capabilities of cores, makes decisions aboutfuture threads to cores mapping. Thread migration isinitiated if the microvisor evaluates that relocating athread to the degraded core will improve performance.Subsequently, PFT in each core is updated with theappropriate thread’s phase information from PHT, and themicrovisor exits. 4.4.1 Instruction-Type Vectors  We propose Instruction-Type Vectors to capture the execu-tion frequency of committed instruction types over aninstruction profiling interval. Instruction types are classifiedinto nine categories:  iALU, iMult, iDiv, iBranch, iLoad, iStore, fpALU, fpMult, fpDiv , where  i  implies integer and  fp  floatingpoint. At the end of each interval, the captured distributionof these instruction types is concatenated to form an ITV. InSection 5, we show that ITVs can be used to classifyrecurring phases in applications. A compressed version of ITV, termed as  ITV Signature  is created to assist microvisorwith ranking threads based on the computational require-ments of phases. To form an ITV signature, the captureddistribution of each instruction type is converted as apercentage of the profiling interval, represented by a 7-bitregister. These 7-bit registers for all instruction types areconcatenated to form a  63-bit ITV signature .Our implementation-independent scheme allows us tocapture the application behavior without any dependenceon the underlying microarchitecture. This makes the phaseclassification process a general purpose online profilingtechnique, which is independent of the underlying hard-ware details, such as capabilities of cores and their memory behavior. 4.4.2 Ranking Threads  The purpose of ranking threads is to find a candidate threadfor mapping to the degraded core. Microvisor uses ITVsignature to extract the expected instruction distributionswithin phases of the threads. Depending on the degradationtype in the faulty core, appropriate categories of the ITVsignature are considered for ranking threads.Therankingprocessisexplainedwithamockupexampleusing Fig. 3. Assume that a Dual-Core CMP has a degradedfloating point unit in one core. Two threads are run on theDual-Core with T1 thread classified with one and T2 threadclassified with two distinct phases. For ranking these threedistinct phases, only floating point related instruction-type 654 IEEE TRANSACTIONS ON COMPUTERS, VOL. 59, NO. 5, MAY 2010 Fig. 2. Microvisor management flow.  distributions are used. Each instruction type is assigned a weight , which is programmable via the microvisor thresholdregisters.AdetailedstudyofhowweightscanbedeterminedispresentedinSection8.2.BasedontheITVsignatureofeachphaseandthread,theinstruction-typedistributionisshown.The rightmost column shows the ranking for each phase,which is calculated by multiplying the weights with theactual instruction-type distributions, and then summing upallcategoriesofITVsignature.Thefinalranking(normalizedto1)showsthattherankofT2-P1isminimum,thusmakingitthemostsuitablecandidateformappingtothedegradedcorewithfaultyfloatingpointunit.Iftherearemultipledegradedcores, ranking is done for each degraded core. 4.4.3 Thread Relocation Policy  The key idea behind microvisor’s thread relocation policy istorelocatethethreadwithminimumrankingtothedegradedcore. This process is repeated whenever a phase change isdetected. In scenarios when the minimum ranked thread isalready mapped to the degraded core or the number of livethreads in the CMP is equal or less than the fully functionalcores, migration is not initiated. When the minimum rankedthread is not mapped to the degraded core, the actual corerunning the minimum ranked thread is selected to swapthreads with the degraded core. When multiple cores areassumed to have distinct degradations, the severity of degradation type is considered in addition to the ranking of threads. The core with most severe degradation is selectedfirst to find a candidate thread followed by rest of thedegraded cores.Weillustrateourthreadrelocationpolicybyextendingtheexample from Section 4.4.1. Assume that thread T2 executesT2-P1 phase for half of its execution and T2-P2 for the otherhalf. The second column in Fig. 3 shows an expectedreduction in CMP throughput when the correspondingthread is mapped to the degraded core. When T1 is mappedto one core, the other core executes the T2 thread until boththreads finish. When T1 is mapped to the degraded core,CMP suffers 10 percent performance loss, whereas when T2is mapped to the degraded core, CMP performance loss is12.5 percent. Microvisor, on the contrary, adapts the threadssuchthatwhenT1-P1andT2-P1phasesareexecuting,theT2is mapped to the degraded core. On the other hand, whenT1-P1 and T2-P2 phases are executing, T1-P1 is mapped tothe degraded core. This results in an overall CMP perfor-mance loss of 7.5 percent, which is the best possibleassignment of threads to cores to achieve minimal perfor-mance loss. 5 R EVEALING  C OMPUTATIONAL  D EMANDS OF T HREADS In this section, we describe the architecture for classifyingthe occurrences of phases in threads using  ITVs . The basicidea is to classify the applications into stable phases andunlock the computational demands of phases. The goal of phase classification is to identify recurring and similarintervals of execution as unique phases. Typical applica-tions incur patterns of recurring behavior with occurrencesof stable and unstable phases. We define the stable phaseas a series of four or more similar intervals, while the restof the intervals are categorized as unstable phases. As thesephases change during runtime, the threads to coresmapping is re-evaluated such that the CMP performanceis maximized in the presence of degraded cores due tohard errors. Our scheme uses a simplified Markov model[24] for predicting phase changes. We also compare ourproposed scheme to a hardware-based phase classificationusing Basic Block Vectors (BBV) [25]. 5.1 Related Work on Program Phase Classification Repetitive and recognizable phases in applications have been observed and exploited by computer architects fordecades [26]. There have been several studies on examiningand classifying program phase behavior at runtime [27],[28]. Programs exhibit phase behavior in terms of Instruc-tion-Level Parallelism (ILP) and instruction mix during thecourse of their execution. It is already well known thatphases may vary significantly across a program [29]. Asprogram phases are rooted in the static structure of aprogram, using an instruction-related model is intuitive.Researchers have used Page working set, Instruction work-ing set, and Basic Block Vectors to describe program behavior [30], [25]. Taking advantage of this time-varying behavior via reconfiguration can enable fine-grain optimi-zations [31]. To make such phase detection feasible, theimplementation has to be low overhead and scalable.Dhodapakar presented a hardware phase detectionscheme based on working set signatures of instructionstouchedinafixedinterval[30].Theinstructionworkingsetishashedintoabitvector,theworkingsetsignature.Theytrackphasechangessolelyuponwhatcodewasexecuted(workingset),withoutweighingthecodebyitsfrequencyofexecution.Sherwood et al. presented a hardware-based scheme usingBBV to track the execution frequencies of basic blockstouched in a particular interval [25]. By examining theproportionofinstructionsexecutedfromdifferentsectionsof the code, BBV is used to find the phases that correspond tochanges in program behavior. BBV shows best sensitivityand lowest variation in phases because it captures code byfrequencyofexecutioninadditiontowhatwasexecuted[28].Although BBV scheme is shown to be quite effective, it doesnot reveal any information about a thread’s computationalrequirements.We propose an Instruction-Type-Vectors-based model,which captures the execution frequency of committedinstruction types over a profiling interval. Using ITV, ratherthan prior schemes, allows exposing the computationalrequirements of a phase in addition to phase classification. KHAN AND KUNDU:  THREAD RELOCATION:   A RUNTIME ARCHITECTURE FOR TOLERATING HARD ERRORS IN CHIP MULTIPROCESSORS 655 Fig. 3. Example of using ITV signatures for ranking threads.
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